Applications
Advanced packaging
Advanced packaging is a system of many process families — we focus on the steps where plasma etch and deposition decide feasibility: through-silicon vias, cavity formation and low-temperature dielectric films.
The process challenges that recur
Vias that fill cleanly
TSV etch is judged by what happens afterwards: profile, scallop and bottom shape determine whether liner, barrier and fill succeed.
Heat-sensitive stacks
Once devices and interconnect are present, every subsequent film must deposit within a tight thermal budget — without giving up density or adhesion.
Competitive, fast-moving supply base
Packaging equipment faces strong local competition. Imported platforms earn their place only on demanding geometries and proven repeatability.
Typical process steps we support
- TSV and interposer silicon etch
- Cavity and pillar formation
- Low-temperature SiO₂ / SiN PECVD
- Stress-engineered dielectric stacks
- Carrier and reconstituted-wafer processing
How we help
Target the hard geometries
We engage where aspect ratio, profile or uniformity requirements exceed what commodity solutions deliver — and are honest when they do not.
Connect etch to fill
Demo criteria defined together with the downstream fill and reliability owners, so the etch result is judged by the integration outcome.
Documentation settled early
Advanced-packaging projects often span several stakeholders. Classification and paperwork are settled at the start, so the schedule holds.
What to prepare for a first discussion
- Integration scheme (2.5D, 3D, WLP, interposer)
- Via dimensions: diameter, depth, pitch
- Wafer type: device, carrier, reconstituted
- Thermal budget and film requirements
- Downstream fill / plating process
- Volume and qualification timeline
Have a structure, film or thermal step to discuss?
Send a short description of your application — device type, material, wafer size and what a good result looks like. An engineer will reply with a concrete next step.