Technologies
Deep silicon etch (Si DRIE)
Deep reactive ion etching produces the high-aspect-ratio silicon structures behind most MEMS devices, silicon photonics benches and through-silicon vias. It is also the process family where marketing numbers and production reality diverge most easily — which makes disciplined evaluation essential.
What it does
Alternating or mixed etch-and-passivation plasma chemistry removes silicon anisotropically, reaching depths from a few microns to through-wafer, at aspect ratios that can exceed 30:1 depending on geometry and process design. Profile, sidewall texture and depth uniformity are engineered outcomes — every application weighs them differently.
Evaluation dimensions that decide projects
- Profile control
- Sidewall angle, bowing, notching at interfaces and corner behaviour — measured on your structure, not a test pattern alone.
- Depth & CD uniformity
- Across the wafer, across pattern densities (ARDE/loading) and from wafer to wafer over a meaningful run.
- Sidewall texture
- Scallop size and roughness where optics, bonding or fill processes demand it.
- Selectivity
- To photoresist, oxide and buried layers — including notching behaviour on SOI.
- Productivity
- Etch rate at your specification, wafer handling, uptime and chamber-matching for multi-chamber production.
Where it is used
Questions worth asking early
Is a headline etch rate meaningful?
Only at your profile and uniformity specification. Rate quoted at relaxed profile requirements can drop sharply once your real acceptance criteria apply — evaluate rate and quality together.
What should a demo include?
Your mask layout or a jointly agreed proxy, written success metrics, cross-section analysis, and repeatability across more than one wafer. A single best-effort photo is not evidence.
Have a structure, film or thermal step to discuss?
Send a short description of your application — device type, material, wafer size and what a good result looks like. An engineer will reply with a concrete next step.